At the moment I’m waiting for my lazy arse lab partner for Digital Electronics Design to turn up so that we can work on our VHDL (Very high speed integrated circuit Hardware Description Language) assignment which is due tomorrow. At the moment we haven’t even tested the program on the FPGA (field programmable gate array) board so we’re not exactly in the best position and I’ve been waiting for over an hour now.
Unfortunately I cant get on without him because he has the FPGA.
Fortunately the damned thing is only worth 10 marks however if we get zero for it I will have to get 96% in the exam to still get an HD.

I am currently using my spare time to work out what I will have to get in the exam for each subject in order to get an HD.

Technical Software Development: 85%
Digital Electronics Design: don’t get know, somewhere between 81% and 96% depending on the assignment.
Engineering Mathematics: 88%
Structural Mechanics: don’t know yet

Distinctions seem more likely than high distinctions for most of my subjects but TSD shouldn’t be too hard to get an HD in.

One thought on “Waiting

  1. Craig June 2, 2006 / 2:59 am

    Help! I suffer from Engineer assumption. See, when I think Engineer, I think Mechanical. Now I’m annoyed at your blog title! Grrr. I should have known better…seen the signs…never to assume when you mentioned structural or was it structured? or did I imagine that… engineering previously, and not to assume you were studying civil/mechanical engineering.The fact that your doing Electrical Engineering makes me want to gag now for some reason… probably because my brother keeps asking me electronics questions and it hurts my brain hearing how silly they are.Hope you managed to get your FPGA all plugged in and smelling of ozone from overexertion.


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